Ballistic to Diffusive Crossover in III–V Nanowire Transistors

In this paper, the authors examine the crossover between ballistic and diffusive transport in III-V nanowire transistors. The authors find that at lower drain voltages the ballistic-to-diffusive crossover occurs at channel lengths of approximately 2.3 nm at room temperature. However, when increasing the drain voltage, the ballistic-to-diffusive crossover can be more than nine times as long at room temperature. As the temperature is decreased, a finding in initially the performance is not significantly improved. However, as the temperature approaches 100 K, the ballistic-to-diffusive crossover increases to longer channel lengths quite dramatically. When InAs, InSb, and InP nanowires are compared at room temperature, the InAs and InSb performance in a similar fashion each with ballistic regions in excess of 10 nm, but that InP has no significant ballistic regime. Finally, simulation of several 10-nm InAs trigate transistors and show that for dopants deeply buried in the source and drain the devices appear ballistic, but when dopants appear near the source-channel interface, significant reductions in performance occur