Lateral scalability limits of silicon conduction channels

We have investigated the lateral scalability limits of the conduction channels in several metal-oxide-semiconductor (MOS) structures, at room temperature, with the goal to understand for which geometries and under which operating conditions a narrow channel approaching the quantum-wire limit can maintain reasonable isolation. A wide range of calculations were carried out using an efficient two-dimensional self-consistent model based on the coupled Schrödinger and Poisson equations. We found that a good trade-off in performance and manufacturability is obtained with a T-shaped gate metallization. Our calculations show that if one uses a highly doped substrate for this system, a quasimonomode quantum wire can be realized at room temperature with a sufficiently high confining barrier. Because of random dopant fluctuations affecting reproducibility and threshold behavior, it would be desirable to eliminate doping in the channel when the width approaches nanometer scale. However, the same MOS structures implemented using an undoped substrate exhibits various problems, the most serious one being a very low confining potential. Considerable improvement is obtained if an undoped layer is grown on top of a highly doped substrate, leading to reasonable confinement and threshold control.