Modeling of FinFET Parasitic Source/Drain Resistance With Polygonal Epitaxy

In this paper, we introduce a new compact model of the parasitic resistance of a FinFET with a hexagonal-shaped raised source-drain (S/D) structure. In contrast to previous models that divided the extrinsic S/D region into three parts, we redefined the region boundaries and modeled them as a series connection of accumulation resistance, gradient resistance, bulk resistance, and contact resistance. The newly added bulk resistance model accounts for the highly doped silicon region. We also significantly improved the contact resistance model to reflect the contact area and contact resistivity for better accuracy in the raised S/D region. We validated the accuracy of our model by varying the gate voltage, doping diffusion length, epitaxy silicon height, and contact resistivity, finding the model errors to be within 2% of the 3-D technology CAD device simulation results.