Short-Channel Performance Improvement by Raised Source/Drain Extensions With Thin Spacers in Trigate Silicon Nanowire MOSFETs

We investigate the short-channel performance of trigate silicon nanowire transistors. Drain-induced barrier lowering at a gate length of 25 nm is strongly suppressed by reducing the nanowire width (WNW) down to 10 nm. We found that the parasitic resistance (RSD) of nanowire transistors is dominated by nanowire-shaped source/drain (S/D) regions under the gate spacer whose resistivity is higher than that in wider regions. We succeeded in significant reduction by raised S/D with thin gate spacer whose width is 10 nm. Although the parasitic capacitance (Cpara) increases by spacer thinning, Cparaincrease is much smaller than RSDreduction, and great performance improvement is obtained for a WNWof less than 15 nm.