Multi-Level GAA FeFET by Multi-Ferroelectric/Dielectric Gate Stacks

The 4-level threshold voltage (VT) and a large memory window of 3V are demonstrated by the Si nanosheet (NS) gate-all-around (GAA) FeFET using multi-ferroelectric (FE)/dielectric (DE) stacks with minimal Si/HZO interfacial layer (IL) and 400oC thermal budget. The three HZO layers are separated by two AlO layers with native oxide removal on Si to favor o-phase HZO growth and to minimize IL for reducing program voltage. The AlO layers trap electrons and pin polarization during program operation. The 4-level VToperation is achieved through layer-by-layer electron detrapping from AlO and polarization depinning at erase operation, confirmed by TCAD simulation. The experimental fast write time of 20 ns, and high endurance >1x108cycles are demonstrated with negligible read disturbance for 4-level VT.