We report 1-3 bit/cell FeFET operation through optimized HSO and HZO ferroelectric laminate layers using alumina interlayers. Memory window up to 3.5V, switching speed of 300ns, 10 years retention, and 10 4 endurance are reported. The gate stack lamination merits are discussed with insight potential of FeFET as an MLC memory.
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Ali et al. (2019) studied this question.
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