Analysis of Fermi-Level Pinning in Silicide/Si Structures with Various Interface Vacancy Defects

As CMOS technologies scale, contact resistance at metal/semiconductor interfaces, particularly silicide/Si, has become a key performance limiter. Although silicide/Si generally exhibits low Schottky barrier heights (SBHs) and weak Fermi-level pinning (FLP), vacancy-type defects can substantially alter interfacial electronic properties. Here, density functional theory (DFT) calculations are performed on silicide/Si interfaces, comparing an ideal interface with three single-vacancy configurations: a metal vacancy in the silicide, a Si vacancy in the silicide, and a Si vacancy in the Si region near the interface. A dilute-defect limit is considered by introducing one vacancy per lateral interface area of the supercell (≈0.0052 Å–2). The results show that FLP is governed primarily by defect location. Vacancies within the silicide suppress interfacial charge redistribution and weaken MIGS-like characteristics, leading to reduced pinning and higher pinning factors (S ≈ 0.51–0.52). In contrast, a Si vacancy on the semiconductor side perturbs near-interface electrostatics and enhances LDOS tails in the Si bandgap, resulting in stronger pinning (S ≈ 0.14). This vacancy-induced modulation of FLP directly translates into systematic shifts in SBHs, providing atomistic insight into defect-mediated FLP in silicide/Si interfaces.