A CMOS folding and interpolating A/D conversion architecture fully compatible with standard digital CMOS technology is described. Fully-differential, continuous-time, current-mode, open-loop analog circuitry is used to achieve high speed. Results from 125 Ms/s 8-b and 150 Ms/s 6-b prototypes implemented in a digital 1 /spl mu/m n-well CMOS process are presented. The 8-b (6-b) converter occupies 4 mm/sup 2/ (2 mm/sup 2/) and dissipates 225 mW (55 mW) from a single 5 V power supply.
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Flynn et al. (1996) studied this question.
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