An area-efficient FPGA-based HOG–SVM architecture for occlusion-aware pedestrian detection in autonomous driving

Pedestrian detection in autonomous vehicles is emerging as a promising solution for reducing road fatalities. The task of detecting pedestrians is challenging due to difficulties like appearances, postures, positions, low visibility, bad weather or occlusion. Hardware implementation of pedestrian detection requires it to be fast, low power and efficient in terms of area. An occlusion-aware pedestrian detection framework is proposed in this work, and it is implemented on Ultra96-V2 Field Programmable Gate Array (FPGA) board. The Histogram of oriented Gradients (HoG) feature extraction algorithm is used along with the Support Vector Machine (SVM) classifier for pedestrian detection. To tackle the challenge of occlusion, the SVM model is self-trained and extracted weights are used in FPGA implementation. To enhance speed, reduce power consumption and utilize less resources, the overall task of pedestrian detection is divided between the Programmable Logic (PL) which handles the computationally intensive processing stages and the Processor System (PS) which is responsible for data acquisition and result formatting. The implemented framework operates on the Ultra96-V2 with a clock frequency of 188 MHz and has a power consumption of 1.9 W. The proposed design employs only 4,998 Look Up Tables (LUTs), 8.5 Block RAMs, 16 Digital Signal Processors (DSP), and 4,031 flip-flops/registers, which collectively account for less than 20% of the total FPGA resources. It achieves a Power Delay Product (PDP) of 10.2 nJ, an Energy Delay Product (EDP) of 54.18 x Js and Area Delay Product (ADP) of 26,549.4 LUT×ns. The Frames per Second (FPS) are reported as 82 for the kernel processing and 11 for the overall system. The obtained performance metrics demonstrate that the developed pedestrian implementation is occlusion aware and is suitable for near real-time pedestrian detection applications.