Analysis and design of an optimum CMRR neural amplifier and a figure of merit for noise and area optimization

The neural amplifier presents one of the key bottlenecks in minimizing the power and area of neural interfaces. The neural amplifier’s power consumption is mainly constrained by the noise requirement, and its area by CMRR and noise. We propose a novel optimum CMRR neural amplifier (OC-NA) based on a capacitively coupled instrumentation amplifier (CCIA) that enhances CMRR and reduces gain mismatch by a factor of A d m / 2 for only 50% increase in capacitor area compared to standard CCIA where A d m is amplifier gain. An analytical model describing the dependence of the CMRR of a CCIA on the ratio of the OTA’s common-mode input capacitance to the feedback capacitor is derived, enabling the selection of the minimum feedback capacitor value without degrading the CMRR. The minimum-value feedback capacitor, area-minimization methodology, and low-mismatch feedback network together minimize area and optimize CMRR and gain mismatch of the proposed amplifier. The post-layout simulation of the OC-NA designed in 180 nm CMOS technology achieves a CMRR of 97 dB mean and 82 dB worst-case without chopping. The OC-NA occupies 0.032 mm 2 area, consumes 3.6 μ W of power, has 0.045% gain mismatch, and 8.36 μ V input referred noise (IRN) with 4.57 NEF. We also propose a reference amplifier-based figure of merit, Noise and area efficiency factor (NAEF), which captures the trade-off between noise and area of the amplifier. The NAEF of an amplifier can be interpreted as the area it occupies for a given IRN relative to the reference amplifier.