Group Delay Time Matched CMOS Microwave Frequency Doubler

In this paper, a frequency doubler using modified time-delay technique is proposed. A voltage controlled delay line (VCDL) in the proposed frequency doubler compensates the group delay time mismatching between input and delayed signal. With the group delay time matching and waveform shaping using the adjustable Schmitt triggers, the unwanted fundamental component() and the higher order harmonics such as third and fourth are diminished excellently. In result, only the doubled frequency component() appears dominantly at the output port. The frequency doubler is designed at 1.15 GHz of and fabricated with TSMC CMOS process. The measured output power at is 2.67 dBm when the input power is 0 dBm. The obtained suppression ratio of , and to are 43.65, 38.65 and 35.59 dB, respectively.