An all-digital built-in self-test for high-speed phase-locked loops

We propose a new structural testing of phase-locked loops (PLLs) using charge-based frequency measurement BIST (CF-BIST) technique. The technique uses the existing charge-pump as the stimulus generator and the VCO/divide-by-N as the measuring device to reduce the area overhead. This approach performs simple dc-like charge injection tests, thus, it is suitable for high-speed PLL applications. Fault simulation results show higher fault coverage than a previous test method with less die area. As no test stimulus is required and the test output is pure digital, low-cost and practical implementation of on-chip BIST structure for a PLL is possible.