Fine pitch Cu/Sn solid state diffusion bonding for advanced three-dimensional chip stacking

Three-dimensional (3D) integration requires vertical stacking of dies while forming permanent electrical and mechanical connections between the input/output pins of the devices. How to enable stacking thermal sensitive devices at low temperature gains interest. This paper presents a systematic study of Cu/Sn bonding at 150–200 °C, during which intermetallic compounds were formed by solid state inter-diffusion. It was found that below the lower-limit pressure of 20 MPa it was hard to make good contact between the rough joint surfaces and hence electrical connection was lost. However, beyond the upper-limit of 150 MPa Sn squeezed out leading to electrical shorting between adjacent bumps. Oxides removal was another key factor for good bonding. Finally, this Cu/Sn solid state diffusion bonding together with Cu through-silicon-via (TSV) was used for making die to die vertical interconnection. The measured resistance of single Cu/Sn solder joint and Cu TSV was in the range of 12–25 mΩ.