Eight-FinFET Fully Differential SRAM Cell With Enhanced Read and Write Voltage Margins

An eight-FinFET fully differential SRAM cell is proposed in this paper to achieve stronger data stability and enhanced write ability. The p-type transistors are used for data access during read operations and transmission gates are employed to force new data into the cell during write operations. At the nominal process corner, the proposed SRAM cell enhances the read data stability, write voltage margin, and write data transfer speed by up to 2.7×, 15.8%, and 76%, respectively, while consuming similar leakage power as compared with the previously published six-FinFET fully differential SRAM cells in 15-nm FinFET technology. Under isodata stability, the proposed SRAM cell allows the lowering of the power supply voltage by up to 44.3% as compared with the other SRAM cells that are investigated in this paper.