This paper presents an eight-element 2-16-GHz programmable phased array (PPA) receiver in a 0.13-μm SiGe BiCMOS with the reconfigurable number of beams and with the digital beamforming (DBF) capabilities. The eight-element chip can be configured for one, two, or four simultaneous beams or as an element-level DBF receiver. This is achieved using reconfigurable input switching and output combining networks with wideband active switches and combiners. The phased array channel results in a 5-b performance at 3-14 GHz (rms error <;5°) and a 4-b performance at 2-16 GHz (rms error <;8.5°). Each channel also contains a 3-b variable gain amplifier with 8-dB gain control at 2-16 GHz. The chip results in an 8-12-dB gain at 2-16 GHz (depending on the PPA mode), a noise figure (NF) of 12 dB, and an input P1 dB of -20 dBm per channel when all channels are activated. The chip consumes 250 mW per channel, which is competitive knowing its bandwidth and linearity. The DBF function also results in a wideband response with a gain and an NF of 15-16 and 12-13 dB, respectively, and high linearity (input P1 dB = -16 dBm) at 2-16 GHz. The programmable phased array receiver allows a single chip to be used over S-, C-, X-, and Ku-bands for a variety of applications such as satellite communications and point-to-point links. This results in faster and lower-cost phased array development since the same chip and its field-programmable gate array control can be reused from system to system, but with different antenna and grid spacing. The PPA removes the need to develop a different chip for every application and allows the development of phased arrays at commercial scales.
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Sayginer et al. (2016) studied this question.
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