Challenges in the Cell-Based Design of Very-High-Speed SiGe-Bipolar ICs at 100 Gb/s

A cell-based design concept for the efficient design of higher integrated SiGe-bipolar circuits operating at data rates equal to or greater than 100 Gb/s is proposed. The performance limitations of circuit designs at these high data rates are discussed with special regard to associated cell-based design aspects. The performances of two cell-based designs are demonstrated by a 100 Gb/s 2:1 multiplexer IC and a 100 Gb/s 1:2 demultiplexer IC with on-chip clock- and data-recovery.