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Selector-only memory (SOM) has attracted attention as a promising memory technology because it enables programmable threshold-voltage state separation using a single ovonic threshold switch (OTS) device. In SOM devices, the electrode–chalcogenide interface strongly affects the threshold-voltage difference (ΔVth) and switching reliability, as repetitive switching induces interfacial reactions and elemental diffusion. In this study, the electrode-dependent SOM characteristics of Ge2Se3Te5 (GST) devices were investigated using W, TiN, and W with an ultrathin (∼6 nm) carbon interlayer (W/C) as top electrodes. The W/C device exhibited the largest ΔVth (∼1.0 V) and the widest read window margin (∼0.9 V), and maintained a ΔVth exceeding 0.7 V over repeated switching cycles, exhibiting the most stable characteristics. Conduction mechanism analysis based on the Poole–Frenkel emission model, Arrhenius analysis, and the thermally assisted hopping model revealed that the enhanced ΔVth originates from increased trap-state separation and trap-density difference between programmed states. Transmission electron microscopy coupled with energy-dispersive X-ray spectroscopy (TEM-EDS) and line-EDS analyses confirmed that the carbon interlayer effectively suppressed Te diffusion and interfacial phase formation at the W/GST interface during repetitive switching. These results demonstrate that ultrathin carbon interfacial engineering is an effective strategy for improving ΔVth and switching reliability in GST SOM devices.
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Kim et al. (2026) studied this question.
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