An 8-Bit Four-Channel Time-Interleaved SAR-Flash Hybrid ADC with Time-Domain Interpolation

An 8-bit 3.2 GS/s four-channel time-interleaved (TI) successive-approximation-register (SAR)-flash analog-to-digital converter (ADC) employing complementary dynamic amplifier (CDA)-based two-step sub-ADCs is presented for high-speed wired and wireless communication systems. Each sub-ADC uses four CDAs to perform a 4-bit asynchronous loop-unrolled (LU) SAR conversion followed by a 4.5-bit reference-embedded interpolating flash (I-Flash) conversion, achieving 8-bit resolution with reduced comparator count and input capacitance. A four-channel TI architecture with a multi-phase clock generator and an on-chip voltage-controlled delay line (VCDL) enables 3.2 GS/s operation while performing foreground offset calibration under full TI loading to accurately track inter-channel reference variations. Fabricated in a 28 nm CMOS process, the prototype ADC shows differential non-linearity (DNL) and integral non-linearity (INL) ranges of −0.78 to +0.74 LSB and −0.84 to +1.03 LSB, respectively, and achieves a signal-to-noise and distortion ratio (SNDR) and a spurious-free dynamic range (SFDR) of 41.74 dB and 58.03 dB at 3.2 GS/s with a Nyquist-rate input. Operating from a 1 V supply, the ADC core consumes 8.63 mW at 3.2 GS/s, corresponding to a Walden figure-of-merit (FoM) of approximately 27 fJ/conversion step.