A TDC-assisted SAR ADC with high-speed sampling switches and fine-tuned delay cells

—This paper presents a 10-bit two-step successive approximation register (SAR) analog-to-digital converter (ADC) based on voltage and time quantization. To reduce S/H circuit leakage current and increase sampling rate at low supply voltage, a new high-speed low-leakage double-bootstrapped sample-and-hold switch (HSLL-DB-SH) is proposed. The LSB gain error between the coarse ADC and fine time-to-digital converter (TDC) are calibrated by fine-tuned delay cells to ensure the gain accuracy. The proposed SAR ADC is fabricated in a 40-nm CMOS with a core area of 0.0363 mm2. The measurement results show the proposed ADC achieved a spurious-free dynamic range (SFDR) of 66.9 dB and a signal-to-noise and distortion ratio (SNDR) of 53.47 dB at 0.5-V supply voltage with a Nyquist input rate at 200 kS/s. The operating frequency scales from 200 kS/s to 5 MS/s. The converter has a power supply range of 0.5–0.8 V, and the figure of merit (FOM) is 9.97–23.17 fJ/conversion-step.