A tunable 8-to-10-bit 140-to-80-MS/s split-capacitor SAR ADC with a time-lag-controlled SAR logic and a power-scalable comparator

A split-capacitor successive approximation register (SAR) analog-to-digital converter (ADC) with tunable 8/9/10-bit resolution has been developed, operating at sampling rates ranging from 140 to 80 MS/s, implemented using 65 nm technology. A new SAR logic topology incorporates time-lag circuits that adjust the conversion time, which increases efficiency and suitability for operations across multiple frequencies. In higher-resolution modes (9 or 10 bits), the sampling rate is reduced, allowing for low-power operation in the comparator. Additionally, a novel power-adaptive comparator, which utilizes a precharged capacitor, ensures reliable decision-making even at lower bias currents. Furthermore, high-speed bootstrapped sampling switches enhance charge transfer by overdriving the gate of the sampling transistor, significantly improving switching performance. Based on the measured results, the ADC demonstrates an effective number of bits (ENOB) of 9.1, 8.2, and 7.3 bits and a corresponding spurious-free dynamic range (SFDR) of 69.7, 64.8, and 59.5 dB at sampling frequencies of 80, 110, and 140 MHz, respectively, while consuming 0.96, 1.1, and 1.3 mW. The proposed ADC occupies an active area of 0.047 mm 2 .