Design of a 10-BIT 100MSPS Sar ADC

This paper reports a 10-bit 100-MS/s SAR ADC using a novel bootstrap switching circuit. The Vcm-based switching time sequence is used to ensure that the comparator has a stable and constant common-mode input voltage during operation. By using split capacitors to avoid the introduction of VDD/2 voltage sources, a segmented DAC array is designed to effectively reduce the capacitance of CDAC. A two-stages dynamic comparator was used to reduce power consumption and noise. At 100M sampling rate and 1.2v supply voltage, the ADC consumes 4.25m W and achieves an SNDR of 60.69dB, resulting in an FOM of 48fJ/Conversion-step. Fabricated in a 40nm 1P6M CMOS technology, the ADC only occupies 0.075mm2 active area.