A Low-Power 10-Bit VCM-Based SAR ADC with 15.4-fJ/conv in 65-NM CMOS

SAR ADC is a type of analog-to-digital converter that uses the successive approximation method to convert analog signals into a digital signal representation. Among them, there are those based on the Voltage Common Mode (VCM-Based) method. These ADCs are the most commonly used both in literature and in the industrial sector due to their greater balance between resolution and conversion speed. Furthermore, they are widely used in a variety of electronic applications, such as communication systems, sensors and measurement instruments. Based on this, this work presents a 10-bit VCM-Based SAR ADC implemented with a capacitive digital-analog converter (CDAC) and sampling using the bootstrapping technique. The VCM-Based SAR ADC developed in this work was designed in a 65-nm CMOS process with a supply voltage of 1.2- V and initially operating at 7.6923 MS/s. The ADC achieves an SNR of 57.66 dB and consumes a total power of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">75.71 μ W</tex> ", resulting in an Effective Number of Bits (ENOB) equal to 9.28-bit and a Figure of Merit (FOM) of 15.83 fJ/conv.