A 14.5-bit Hybrid SAR and Single-Slope Analog-to-Digital Converter with Background Calibration and a Low-Noise Comparator

Abstract This paper presents a hybrid of successive approximation register (SAR) and single-slope (SS) ADC with digital background calibration, achieving a resolution of 14.5 bits. The design combines the benefits of SAR and SS ADCs, utilizing SAR for coarse 7.5-bit quantization and single-slope ADC for fine 8-bit quantization with one redundant bit included between two stages. The proposed digital-to-analog capacitor (DAC) switching method reduces power consumption during the SAR quantization phase and minimizes the size of the DAC array. Additionally, a new comparator design is proposed, which operates in high-speed mode at the SAR phase and in low-noise mode at the SS phase, respectively. Operating at a sampling rate of 100 kS/s and with a 1.6 Vpp input signal, the measured SNDR, SFDR, and ENOB achieve 69.01 dB, 78.50 dB, and 11.17 bits, respectively, while consuming power of 40 µW at a 1.8 V power supply. With background calibration implemented in an off-chip FPGA, the FoM reaches 24.4 fJ/conv.-step.