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Vacuum and hermetic packaging is a critical requirement for optimal performance of many micro-electromechanical systems (MEMS), vacuum electronics, and quantum devices. However, existing packaging solutions are either elaborate to implement or rely on bulky caps and footprint-consuming seals. Here, we address this problem by demonstrating a waferlevel vacuum packaging method featuring transfer bonding of 25-μm-thin silicon (Si) caps that are transferred from a 100-mm-diameter silicon-on-insulator (SOI) wafer to a cavity wafer to seal the cavities by gold-aluminum (Au-Al) thermocompression bonding at a low temperature of 250 °C. The resulting wafer-scale sealing yields after wafer dicing are 98% and 100% with sealing rings as narrow as 6 and 9 μm, respectively. Despite the small sealing footprint, the Si caps with 9-μm-wide sealing rings demonstrate a high mean shear strength of 127 MPa. The vacuum levels in the getter-free sealed cavities are measured by residual gas analysis to be as low as 1.3 mbar, based on which a leak rate smaller than 2.8 × 10-14mbarL/s is derived. We also show that the thickness of the Si caps can be reduced to 6 μm by post-transfer etching while still maintaining excellent hermeticity. The demonstrated ultra-thin packages can potentially be placed in between the solder bumps in flip-chip interfaces, thereby avoiding the need of through-capvias in conventional MEMS packages.
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Wang et al. (2019) studied this question.
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