Two-Bit/Cell NFGM Devices for High-Density NOR Flash Memory

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the VSUPth/SUP margin for 2-bit/cell operation by ~2.5 times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the VSUPth/SUP margin more than ~1.5V. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better △VSUPth/SUP and VSUPth/SUP margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ~10 nm below the source/drain junction.