Reliability Study of MOS Capacitors Fabricated on 3C-SiC/Si Substrates

This is the authors' abstract. We don't add key points for this paper.

3C-SiC technology has advanced a lot in the last decade and the interests in making 3C-SiC power devices are growing again, in research and industry. Despite of that, there has been a lack of knowledge on the reliability of the 3C-SiC MOS structure. In this paper, we investigated the MOS capacitors fabricated on 3C-SiC/Si substrates at room temperature. From the simple I-V characterisation, an effective barrier height as high as 3.65-3.71 eV can be extracted for the fabricated 3C-SiC/SiO2 interface. Reliability test under elevated gate bias which lasts weeks demonstrates an acceptable failure rate (3450 PPM) for these state-of-the-art 3C-SiC MOS capacitors. The failure mechanism study suggests the intrinsic region is still not reached and there is still much room to improve the reliability. Minimising some obvious extrinsic defects which lead to early breakdown alone can reduce the failure rate by 100 times.