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We fabricate 128 Kbit SRAMs using a rad-hard circuit design based on a mixed-mode three-dimensional simulation in a commercial silicon-on-insulator foundry with 0.2 /spl mu/m design rules. Appropriate design increases the critical linear energy transfer of single-event upset over 164.4 MeV/(mg/cm/sup 2/).
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Hirose et al. (2002) studied this question.
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