Preliminary Measurement Results of a 650 GHz Planar Circuit Balanced SIS Mixer

We present the design and preliminary experimental results of a broadband 650 GHz balanced SIS mixer utilizing two back-to-back unilateral finline tapers. The new design employs fully integrated circuit components onto a 15 μm silicon-on-insulator (SOI) substrate, hence greatly simplifying the balanced mixer block requirements. Independent testing of the on-chip RF quadrature hybrid and the DC/IF blocks showed performances consistence with the computational predictions. The fabricated mixer chip tests have also demonstrated successful operation in balanced mixing mode as the LO noise was separated from the IF output. Preliminary tests of the device's sensitivity gave a best double sideband (DSB) noise temperature of 714 K measured at 635 GHz, and remained at a similar level throughout the operating frequency band. The higher than expected noise temperature was mainly caused by a significant shift in the junction position during fabrication, in both the longitudinal and lateral directions, resulting in substantial shift in the tuning frequency and degradation in the coupling of power to the junction.