Circuit design study demonstrates 80.4 dB SNDR with 0.656 µW power in a 14-bit SAR ADC, highlighting viable ultra-low-power sensing for biomedical devices.
DAC mismatch is a major challenge for high-resolution ADCs. This brief proposes an analog-detection-based input range compensation technique for high-resolution ADCs with mismatch error shaping (MES). By applying a pre-comparison and suitably switching the DAC MSB, the input loss caused by MES is compensated. By adopting a flying-capacitor sampling technique, the prediction errors found in prior solutions are avoided. The prototype 14-bit SAR ADC achieves 80.4 dB SNDR and 93 dB SFDR in a 4 kHz signal bandwidth with an OSR of 16. It only occupies 0.0034 mm2 and consumes0.656~μ Wunder a 0.8 V supply, leading to a Schreier figure-of-merit of 178.3 dB. These features make it suitable for miniaturized high-performance IoT and biomedical systems.
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Shen et al. (2023) studied this question.
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