Deep level transient spectroscopy and capacitance-voltage study of dislocations and associated defects in SiGe∕Si heterostructures

Three SiGe∕Si heterostructures with different Ge contents have been examined by deep level transient spectroscopy (DLTS) and capacitance-voltage techniques. DLTS revealed a broad band of traps from 80to250K in the as-grown samples. Arrhenius plots of a 25% SiGe sample revealed three trap levels at 0.28, 0.31, and 0.43eV above the valance band, respectively. By varying the reverse biases and comparing samples of different Ge contents, it was found that the trap levels shift toward the valance band with increasing Ge concentration. Capacitance-voltage data indicated that the acceptor trap levels in the SiGe graded layer dramatically decreased from 40×1013cm−3 in the as-grown sample to 4×1013cm−3 after annealing at over 800°C. Based on their charge states and thermal annealing behaviors, we suggest that majority of the grown-in acceptor levels are likely due to vacancy clusters generated by dislocation jog dragging, which can be readily annealed out, leaving only the dislocation related deep levels. The density of deep levels along a relatively clean dislocation is estimated to be ∼104cm−1.