Design and feasibility of strain FET based on TMD heterostructure

Electrostrictive materials and devices have been widely explored for information processing and storage devices. Electrostrictive field-effect transistor (E-FET) is an emerging steep-slope device concept which could allow low-power logic operations. However, E-FET has not been experimentally demonstrated yet, largely due to a gap in fundamental knowledge of constituent materials that meet the device requirements. Here we propose to adopt 2D materials as a backbone of E-FET that consists of a piezoelectric TMD (transition metal dichalcogenide) monolayer interfaced with another TMD channel layer. By performing literature-benchmarked finite-element simulations on various TMD heterostructures, including the flagship material stack of MoS 2 /PtSe 2 , we show that the application of a nominal gate voltage to the piezoelectric 2D layer can induce compressive stress as high as 10 7 N/m 2 on the adjacent 2D channel layer. C-AFM (conductive atomic force microscopy) is also carried out to experimentally prove that this stress can cause reversible modulation of conductance for the 2D channel layer (PtSe 2 ). From the phase diagram analysis that simulates both the stress and electric potential distributions inside the piezoelectric 2D layer, the stress is found to be the largest at the interface with the 2D channel layer. A scaling study is also conducted by varying the thickness of both 2D layers to ultimately guide experimental researchers through the design and manufacturing of strain-based FETs based on 2D materials.