A 100-GHz 0.21-K NETD 0.9-mW/pixel Charge-Accumulation Super-Regenerative Receiver in 65-nm CMOS

In this paper, a charge-accumulation technique is proposed in the design of super-regenerative receiver (SRR), which significantly improves the receiver responsivity and sensitivity. Furthermore, a new power-injection method is adopted without loading the $LC$- tank of super-regenerative oscillator (SRO). Implemented in a 65-nm CMOS technology with a core area of 0.023 mm2, the prototype achieves a sensitivity of -67 dBm, a noise-equivalent power (NEP) of 2.8 fW/Hz0.5, and a noise-equivalent time difference (NETD) of 0.21 K with a power consumption of 0.9 mW.