The network-on-chip (NoC) is an enabling methodology to integrate many embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of multi-hop links used in data exchanges. To address these problems, this paper introduces design methodology for a wireless NoC with multiple nonoverlapping channels. The authors present both the physical layer design and the overall interconnection architecture.
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Yu et al. (2014) studied this question.
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