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This brief presents a low-noise K-band phased array receive channel implemented in a 130-nm SiGe BiCMOS process. The IC consists of a cascode LNA, a vector modulator phase shifter (PS), and a current-steering VGA. The LNA employs a shunt inductor at the intermediate node of the cascode for noise reduction purposes. The PS generates I/Q signals by lumped quadrature hybrids for low noise operation. Various process compensation capabilities are employed within the PS to reliably achieve high resolution. The measured results demonstrated a peak gain of 28.5 dB at 24 GHz with a 3-dB bandwidth of 22-27 GHz. The measured noise figure is 3.3 dB, which is better than state-of-the-art among Si-based phased-array channels. For 6-b phase control, the rms phase error is 4° and 0.2° without and with calibration, respectively; the rms gain error being 1 dB for both cases. For 4-b gain control with 0.4-dB/step, the rms amplitude/phase errors are 0.1-dB/0.5°. Across different phase settings, the IC has an OP1dB of -2 to -3 dBm, with a power consumption of 48 mW. The total chip area is 1.33 mm2, excluding the pads.
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Kalyoncu et al. (2020) studied this question.
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