A 42-dBΩ~25 -Gb/s CMOS Transimpedance Amplifier With Multiple-Peaking Scheme for Optical Communications

This brief presents a low-power, broadband, inverter-based transimpedance amplifier (TIA) design employing the input series peaking and shunt-shunt inductive feedback in a 65-nm CMOS process. The design optimization of the TIA core amplifier is described in detail. The proposed multiple-peaking scheme incorporates an input bond-wire and two on-chip inductors to mitigate the photodetector capacitive loading, achieving an overall bandwidth enhancement ratio of 2.8. A transimpedance gain of 42 dBQ is measured up to 24 GHz without the off chip photodetector capacitance. A low-dropout regulator (LDO) with full-spectrum power supply rejection is integrated to suppress supply noise and parasitic effect due to the power supply bond-wires. Optical measurements at 25 Gb/s show that the data eye RMS and peak-to-peak jitters are improved by 15% and 24%, respectively, when the LDO is enabled. The measured TIA sensitivity is -7.3 dBm at 25 Gb/s with a BER-12for a 215-1 PRBS optical input. The 1-V TIA with on-chip LDO consumes 3 mW from a 1.2-V external power supply.