Automatic Generation of Symbolic Reliability Functions for Processor-Memory-Switch Structures

Calculation of the reliability of computer system architectures with built-in redundancy, such as multiprocessors, is gaining in importance. The task of computing the reliability function for arbitrary Processor-Memory-Switch (PMS) interconnection structures, however, is tedious and prone to human error. Existing reliability computation programs make one of two assumptions: • That the case analysis of success states of the system has been carried out. Such analysis must be done manually. In this instance, input to the program is usually in the form of an intermediate representation (e.g., fault tree, reliability graph). • That the interconnection structure is a member of, or can be partitioned into, some limited class of structures for which a parametric family of equations exists (e.g., N-modular redundant systems, hybrid redundant systems).