SET Characterization and Mitigation in 65-nm CMOS Test Structures

SET propagation and mitigation in 65-nm CMOS test structures are investigated. Radiation tests showed a clear distortion of the SET pulse-widths related to the structures' design and layout as well as the efficacy of the employed mitigation techniques. Recommendations are provided to designers to simulate their designs to radiation effects, accounting for their layout and routing switches in the case of FPGAs. A special attention was also given to the trade-offs between charge sharing and charge collection efficiency of the first ion hits on a CMOS node that will greatly impact the final propagated SET pulse width in a given circuit layout.