A Low-Power Capacitorless LDO Regulator with Transient Enhancement Structure

This is the authors' abstract. We don't add key points for this paper.

In this paper, a portable low-power low dropout regulator (LDO) with no output capacitance has been designed in 0.18-[Formula: see text]m CMOS technology. In this paper, a PMOS power transistor is used and combined with an overshoot and undershoot suppression circuit to improve the transient response of the circuit. A modified Class-AB operational transconductance amplifier (OTA) is used to reduce power consumption and act as an error amplifier to eliminate low frequency poles. At the same time, a super source follower and a Miller capacitor are used for frequency compensation of the system. Finally, the system can provide a stable voltage for a load step from 0.2 to 25[Formula: see text]mA in 500[Formula: see text]ns edge-time for 140[Formula: see text]pF-load capacitance. The test results show that the circuit achieves a good voltage regulation rate and high transient response.