Novel LDO demonstrates improved transient response and efficiency in voltage regulation, indicating significant advances in integrated circuits.
Improving the transient response performance is a critical challenge in low-dropout regulator (LDO) design. This paper proposes a novel on-chip capacitor-less LDO based on substrate technology implemented in an SMIC (Semiconductor Manufacturing International Corporation) 0.18 μm CMOS (complementary metal oxide semiconductor technology) process. Central to this innovation is a fast response loop between the PMOS driver’s body and gate, which leverages the body effect to enhance driver control without complex bulk-driven techniques. The proposed LDO achieves a quiescent current of 4.5 μA, an efficiency of 88%, an overshoot/undershoot of 12mV/22mV, and a settling time of 1.2 μs. The comparative analysis confirms that this structure increases the maximum load current and reduces the loop response time relative to those for conventional LDOs. These results validate a significant improvement in the transient performance, marking an important advance in integrated voltage regulator technology.
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Li et al. (2025) studied this question.
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