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This paper investigates a parallel multilevel current source inverter (CSI) for low-voltage to medium-voltage (LV/MV) photovoltaic (PV) power conversion based on 3.3 kV SiC MOSFET and dedicated space vector modulation (SVM) schemes. A design-oriented sizing tool is developed to evaluate semiconductor losses, junction temperatures, and conversion efficiency across the full maximum power point voltage (VMPP) range (≈850–1450 V) of a 1.5 kVDC open-circuit voltage (VOC) PV string for three-, five-, and seven-level configurations, accounting for synchronous rectification mode (SRM) constraints, whereas experimental validation was performed exclusively on a two-block (five-level) prototype. Numerical analysis demonstrates that power building block shedding (PBBS), i.e., the sequential activation of parallel CSI matrices, improves European efficiency by approximately 0.19% in this specific configuration compared to the defined seven-level operation while maintaining device junction temperatures within acceptable thermal limits. A CL output filter is sized to target WTHD below 3% over the operating envelope. A two-block (five-level) prototype demonstrates LV/MV conversion up to approximately 4.2 kW, validating the proposed SVM sequence. Since experimental operation was conducted under worst-case conduction losses (non-SRM) due to testbench safety constraints, a full performance evaluation could not be completed at this stage.
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Gomez et al. (2026) studied this question.
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