Three SoCs in Three Years: How to Get Agile

We taped out three large system on chips in three years on 22-nm CMOS technology, featuring multiple RISC-V cores, and subsystems for machine learning, Ethernet, SerDes, Low-Power SDRAM, and input–output. We have covered all steps in the flow from specification to sample chips. Ballast, Tackle, and Headsail include 130 M, 12 M, and 340 M transistors and took 12, 10, and nine calendar months. Several persons from seven companies and university contributed to the three chips, and staff ranged from experts to novice master students. This article provides insight into modern fast-paced system-on-chip hardware (HW) development which is important when intellectual properties such as RISC-V processors and security accelerators are evolving rapidly. We achieved Agile development with the following guidelines: intellectual properties elaborated on the go, staff moves along the design flow, interface over instance, and schedule over features.