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Charge collector damage, caused by process‐induced charging of thin gate oxide capacitors, is a crucial yield and reliability limiter for submicron technology. Wafer level testing on a unique set of test structures shows that charge collector ratios of exposed and buried conductive collectors is important in determining the amount of degradation. Various equipment and processes such as resist strip, plasma etch, sputtering, and ion implantation are evaluated and improvements made to create a robust fabrication environment. A new model, incorporating the charge‐sharing model and the new "charge strike" defect density model, is used to explain how charge collector damage occurs and is evaluated vs. experimental data.
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Greene et al. (1992) studied this question.
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