Several VLSI architectures for performing exponentiation in GF(2/sup m/) are presented. Two approaches to the architecture design are taken. In the first, all intermediate products of the exponentiation are computed in a sequential fashion to minimize the silicon area. In the second approach, all values of raised to the 2/sup ei/ power, O>
No takes yet. Share an insight, caveat, or question.
Scott et al. (1988) studied this question.
Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context: