A new low-cost concept for a system-on-chip Bluetooth solution is proposed in this paper. The single chip includes all necessary baseband and RF parts to achieve full Bluetooth functionality and is implemented in a standard 0.25-/spl mu/m CMOS technology. The two-point modulation /spl Sigma//spl Delta/ fractional N phase-locked loop achieves a phase noise of -124 dBc/Hz at 3-MHz offset. The sensitivity of the embedded low-IF receiver is measured to be -82 dBm at a bit error rate of 0.1%. The power supply voltages for the digital and analog parts are internally regulated to 2.65 V. The maximum current consumption of the analog part is 60 mA.
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Durdodt et al. (2001) studied this question.
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