An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS

This paper presents a 12-bit dual-residue pipeline ADC allowing the use of low gain and low bandwidth residue amplifiers to achieve 59 dB peak SNDR at 800 MSample/s. The dual-residue architecture is insensitive to the open-loop gain and the bandwidth of the residue amplifiers. However, their offset limits the accuracy of the entire ADC and therefore a background offset calibration technique was implemented. The high sampling speed was obtained through four times interleaving, requiring gain and offset calibration between the interleaved ADC lanes. The ADC was realized in a standard 40 nm CMOS technology, operates from a dual 1 V/2.5 V power supply, utilizes an input range of 1.2 V peak-to-peak differential, and consumes 105 mW.