An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree

RRAM is a promising candidate to implement large-capacity in-memory computing on edge AI devices due to its high density. However, the efficiency and accuracy of RRAM-based computing-in-memory (CIM) works are limited by large accumulation currents and device variations. The SRAM-based digital CIM achieves superior performance and efficiency while the adder tree dominates the area. In this brief, a digital RRAM CIM macro is proposed to achieve a better trade-off between accuracy, energy, and performance by three techniques. First, a dynamic voltage sense amplifier is designed to reduce >90% read currents of low resistance state (LRS) cell. Second, an OR gate approximate adder tree is proposed to reduce the area of the adder tree by 40%. Third, a sparse-aware finetuning algorithm is proposed to reduce the accuracy loss of approximate arithmetic to 0.4% on Cifar-10 dataset. The proposed design achieves 1966TOPS/W energy efficiency and 51.2GOPS/Kb normalized throughput at 1-bit precision which is1.2×and1.8×higher than previous RRAM-based designs. This brief demonstrates the advantage of digital CIM using RRAM devices.