Heavy-Ion Soft Errors in Back-Biased Thin-BOX SOI SRAMs: Hundredfold Sensitivity Due to Line-Type Multicell Upsets

Silicon-on-insulator technology is often used to develop high-reliability devices with low sensitivity to single-event upsets or soft errors. Its key component, the buried-oxide (BOX) layer, is now thinned down to 10 nm. This thinning enables transistors on the layer to be efficiently conditioned by back-bias voltages fed underneath the layer. However, a little is known about the influence of such conditioning on the sensitivity to soft errors caused by heavy ion radiation. A static random access memory supported by a 10-nm-thick BOX layer was exposed to high-energy heavy ions. Back-bias voltages were fed to the memory cells through a triple well structure fabricated underneath the BOX layer. The applied back-bias conditioning led to a 100-fold increase in the soft-error sensitivity compared with the counterpart zero-bias condition. In addition, interesting line patterns of the upset cells were revealed on the memory floor. These findings are contrary to previous results in neutron and alpha-particle tests. Analyses and modeling as well as supplementary gamma-ray total ionizing dose tests suggest that they are caused by a new soft-error mechanism. Back-bias conditioning may increase perturbations in potential under the BOX layer, which are originally induced by respective single heavy-ion strikes. Each perturbation may spread under the layer and cause multiple cells on the layer to be upset via the capacitance coupling principle.