A new two-dimensional (2-D) numerical simulation model for the solid-phase-crystallized polysilicon (poly-Si) thin-film transistors (TFTs) is presented in this paper. The proposed model is mainly based on the defects located at the poly-Si/gate oxide and poly-Si/buffer oxide interfaces and at the intergrain boundaries. The simulation results have shown to be consistent with the experimental TFT data. It has been demonstrated that the interface/grain boundary trap states have different effects on the conduction mechanisms of the poly-Si TFTs. The characteristics of the poly-Si TFTs are discussed in detail.
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Chou et al. (1999) studied this question.
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