Low-Power Analog CMOS Implementation of a Spiking Neural Network for Reservoir Computing Applications

With the rapid growth of deep neural networks, the increasing power consumption of AI hardware has become a critical issue, especially for edge devices that require real-time processing under strict energy constraints. In this context, spiking neural networks (SNNs) have attracted attention because they process information using sparse spike events and naturally incorporate temporal dynamics. Analog circuit implementations can further improve energy efficiency by exploiting continuous-time device physics, such as subthreshold transistor characteristics, enabling compact realization of neural computation with reduced circuit complexity. In addition, event-driven operation allows unnecessary computation to be suppressed when spikes are absent, which is well suited for low-power systems. Based on these advantages, this paper introduces fundamental principles of SNNs and discusses key circuit building blocks for analog neuron and synapse implementations. Furthermore, the application of analog SNN circuits to reservoir computing is described as an effective framework for time-series information processing, where rich nonlinear dynamics can be utilized while simplifying the learning process. Finally, system-level considerations and potential applications for edge devices are discussed, highlighting the feasibility and future prospects of analog CMOS-based neuromorphic computing.