Stochastic Resonance Exploitation in Sub-Threshold CMOS Logic for Ultra-Low-Power Neural Signal Decoding

This is the authors' abstract. We don't add key points for this paper.

In this work, the notion of stochastic resonance (SR) and sub-threshold complementary metal-oxide-semiconductor (CMOS) circuit design is presented as an intriguing paradigm for extremely power-constrained neural signal decoding in implantable biomedical systems. In this paper, the notion of stochastic resonance (SR) with the concept of sub-threshold complementary metal-oxide-semiconductor (CMOS) circuit design is combined to present an interesting paradigm for extremely power constrained neural signal decoding in implantable biomedical systems. In this paper, the authors review some fundamental and current research to explore the potential for improving weak sub-threshold neural signal detection in energy limited analog front-end circuits by controlling the injection of noise. In a nonlinear system, when noise is added at an optimal level, the phenomenon of SR, first introduced by Benzi et al. [1] and later expanded by Gammaitoni et al. [4] refers to an increase in the detectability of the signal. Sub-threshold CMOS circuits that run below the traditional 1.0V supply voltage have transistor behavior similar to that of biological neurons, making them ideal candidates for exploitation of SR. A 12–18 dB reduction in the signal-to-noise ratio (SNR) has been shown from the study of hippocampal neurons [14, 15], and circuits with power dissipation as low as 75 nW have been reported [8]. Consumption of less than 2.7 μW with noise efficiency factor (NEF) < 4.0 [17] for neural recording amplifiers further supports the scalability of this approach. This paper introduces a systematic study of SR mechanisms for nonlinear CMOS threshold systems, comparison of sub-threshold amplifier topologies, and a unified approach to designing SR-based neural decoding architectures. The key quantitative results show that by using SR decoding, the detection improvement ranges from 15 to 23 per cent when the voltage supply is between 0.3 and 0.5 V compared to using conventional decoding methods, while an energy efficiency gain of up to 60% is possible when SR is exploited intentionally instead of being tolerated.